1. Field of the Invention
The present invention relates to a nonvolatile memory cell, a nonvolatile memory array and a method of operating the same, and more particularly to a nonvolatile memory cell and/or array and a method of operating the same enabling high integration density, low voltage programming and/or high speed programming.
A MNOS memory is one of typical semiconductor memories wherein carrier charge is stored in a gate insulator to have information nonvolatilely stored. The MNOS memory is of a laminated structure comprising a conductive gate (M), a silicon nitride film (N), a tunnel oxide film (O) and a semiconductor wherein the carrier (electron or hole) is captured at a trapping level in the silicon nitride film to store the carrier charge. In this step, the silicon nitride film of the MNOS memory was required to be more than 19 nm in thickness since the charge trapping efficiency depended on the carrier capture distance in the silicon nitride film (Document 1: F. L. Hampton and J. R. Cricchi xe2x80x9cSpace charge distribution limitation of scale down of MNOS devicesxe2x80x9d, 1979 IEDM Technical Digest, p. 374).
To program (write or erase) the MNOS memory, at least more than 10V or about 20V as a normal value of programming voltage was required for a electric field to be fed to a semiconductor surface via the silicon nitride film so that a carrier may be injected in the nitride film through (via a tunnel) the tunnel oxide film.
Also, a MONOS memory is disclosed as the nonvolatile memory capable of reducing the programming voltage (Document 2: E. Suzuki, H. Hiraishi, K. Ishii and Y. Hayashi, xe2x80x9cA Low-Voltage Alterable EEPROM with Metal-Oxide-nitride-Oxide and semiconductor (MONOS) Structuresxe2x80x9d, IEEE Transaction on Electron Devices, Vol. ED-30, February 1983, p. 122). This MONOS memory is of a laminated structure comprising a conductive gate (M), a top oxide film (O), a silicon nitride film (N), a tunnel oxide film (O) and semiconductor. This structure has enabled the MONOS memory to stop hopping via the carrier trapping level in the silicon nitride film due to a potential barrier formed between the nitride film and the top oxide film, which resulted in making the nitride film as thin as possible. Further, carrier traps newly generated at the interface between the top oxide film and nitride film has enlarged a memory window to the extent it is possible to identify the stored information even if the entire insulator thickness is made thinner.
This MONOS memory has made it possible to reduce the programming voltage down to 9V with the usable programming speed (0.1 msec) under the condition that the stored information is maintained for ten years (Document 3: T. Nozaki, T. Tanaka, Y. Kijiya, E. Kinoshita, T. Tsuchiya and Y. Hayashi, xe2x80x9cA1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Applicationxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April, 1991, p. 497).
It has yet to be disclosed, however, whether or not it is possible to reduce a programming voltage to be less than 9V under the condition that the programming speed is less than 0.1 msec and memory retention characteristics are maintained. To achieve the programming voltage of less than 9V, either programming speed or memory storage characteristics or both were required to be sacrificed.
Disclosed is a technology to integrate a single transistor cell with a single gate (to be connected to a word line) in the form of an array to improve integration density which is more excellent than that disclosed in the Document 3 as described above. However, since it was required to supply electrical potential to not only a drain region but also a source region so as not to write in an unselected cell which results in separately connecting both drain and source regions to a bit line direction, it was impossible to improve the integration density even if a single gate structured single transistor cell is used therein. (Document 4: 1. Fujiwara, H. Aozasa, A. Nakamura, Y. Komatsu, and Y. Hayashi, xe2x80x9c0.13 xcexcm MONOS single transistor memory cell with separated sourcexe2x80x9d, 1998 IEDM Technical Digest, 36.7, p995-998, FIG. 2 and 11).
When integrating a single gate cell in the form of an array to read the stored information, there is deterioration of memory retention characteristics called xe2x80x9cread disturbxe2x80x9d since electrical potential for reading the stored information is to be supplied to a gate.
To prevent the deterioration of the retention characteristics as described above and to keep the stored information well trapped even in the state of electrical potential being supplied to a gate, it was required to increase the thickness of the above-indicated tunnel oxide film from 2.0 nm to 2.7 nm. To make as minimal as possible the programming speed deterioration due to the increase of a tunnel oxide film thickness, it was necessary to increase programming voltage from 9V to 12V.
Meanwhile, disclosed is technology of ballistic carrier injection for a floating gate memory cell which is intended to enable reduction of programming voltage and increase of programming speed (Document 5: S. Ogura, A. Hori, J. Kato, M. Yamanaka, S. Odanaka, H. Fujimoto, K. Akamatsu, T. Ogura, M. Komiya and H. Kotani, xe2x80x9cLow voltage, Low current, High speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flashxe2x80x9d, 1998 IEDM Technical Digest, 36.5, p.987-990). The ballistic carrier injection as described above has such a configuration that formed in the form of a step in a surface of a semiconductor substrate is a thin drain region through which a hot carrier is ballistically transported to a floating gate and the floating gate is disposed to cover the step portion. This improves the injection efficiency since the speed component in the carrier transport direction contributes to generating energy for the carrier injection.
However, the carrier injection and discharge of a conventional MONOS nonvolatile memory are carried out in an entire surface of a channel forming a semiconductor region beneath a gate insulator in which carrier charge trapping function is incorporated and it was not known from the carrier injection in a floating gate memory cell whether or not current or voltage sensed at time of reading the memory cell was controlled by the carrier charge in the gate insulator trapped by local carrier injection in source/drain directions in a channel forming semiconductor region. Neither was it possible to clearly read that the carrier charge injected through the above-mentioned thin drain resulted in changing current and voltage in the conventional MONOS nonvolatile memory.
With respect to a conventional floating gate memory, it is liable to cause defective bits if even one location of a gate insulator is found to be defective which results in deteriorating the memory retention characteristics of an entire cell. In addition, the ratio of the total capacitance of a floating gate to the capacitance between a control gate and floating gate decreases as a memory structure becomes fine. To eliminate the disadvantage as described above, it was required to adopt such a structure as to increase the overlapped area between the control gate and floating gate and further, there was no choice but to increase a number of manufacturing process steps and cell area.
It is a purpose of the present invention to resolve problems in the conventional technology and provide a nonvolatile memory cell which is not only capable of programming with lower voltage but also has a remote possibility of causing defective bits and has fewer manufacturing process steps compared to a conventional floating gate memory; a method of using the same and a nonvolatile memory array.
To achieve the purpose as described above, the present invention is provided with the means featured below:
A nonvolatile memory cell wherein first and second impurity regions of opposite conductivity type are formed in a main surface of a substrate and separated therebetween by a channel forming semiconductor region of one conductivity type in the main surface of the substrate and a gate electrode is formed on a gate insulator on the channel forming semiconductor region, carriers being injected and stored in a carrier trapping means of the gate insulator further comprising:
(a) provided is an acceleration-electrical potential supplying means to selectively supply the acceleration-electrical potential to one out of the first and second impurity regions at one side;
(b) the channel forming semiconductor region includes a carrier-supplying portion and carrier-acceleration-injection portion disposed along the carrier transport direction;
(c) the carrier-supplying portion supplies to the carrier -acceleration-injection portion carriers supplied by the other one out of the first and second impurity regions at the other side; and
(d) the carrier-acceleration-injection portion makes local injection of carriers supplied from the carrier-supplying portion into the gate insulator in the vicinity of the adjacent other one out of first and second impurity regions at one side to which the accelerated electrical potential is supplied: and
(e) the gate insulator is provided with at least a carrier charge trapping means in a projecting area of the carrier-acceleration-injection portion.
According to the features as described above, a space charge region is extended from a second impurity region to a carrier-acceleration-injection portion by electric field due to electrical potential supplied to a second impurity region. Out of carriers supplied to the carrier-acceleration-injection portion, energy is supplied by the electrical potential difference in the space charge region to a carrier which is moved as far as near the interface with the second impurity region without being affected by lattice scattering and the aforesaid carrier is injected, that is, locally injected in a very narrow region of the carrier charge trapping means getting over a potential barrier formed at the interface with the gate insulator.
More particularly, it is possible to supply to a carrier energy getting over the potential barrier VB between a gate insulator and carrier-acceleration injection portion with the distance three times the mean free path of a high energy carrier by disposing a carrier-acceleration-injection portion in a channel forming semiconductor region. The shorter the distance within which energy is supplied to a carrier (and which generates electrical potential difference of VB), the more the carrier number getting over the electrical potential increases. However, as the distance becomes shorter, probability of a carrier tunneling increases due to high electric field and the lower limit of the distance is determined as a value (near to the aforementioned three times the mean free path of a high energy carrier) to prevent the useless current increase due to the increase of the carrier tunneling. If the distance within which the energy is supplied to the carrier (which generates the electrical potential difference of VB) exceeds fourteen times the mean free path of the high energy carrier, the injection efficiency is almost the same as that of the conventional channel hot electron injection.
Meanwhile, it is possible to read the information trapped in a cell by detecting a cell current or cell threshold voltage even if a carrier charge is not trapped in an entire region of a gate insulator having carrier charge trapping function. For example, it is possible to read the information if the carrier charge is trapped in a length (to the direction connecting a first impurity region and second impurity region) of the gate insulator which is more than 20 nm long out of gate insulators.